[all-commits] [llvm/llvm-project] c8f20e: [AArch64][SVE] Move convert.{from, to}.svbool optim...

[Bradley Smith via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c8f20ed44888f3a09c077690480d1d978c881b0d
      https://github.com/llvm/llvm-project/commit/c8f20ed44888f3a09c077690480d1d978c881b0d
  Author: Bradley Smith <bradley.smith at arm.com>
  Date:   2021-04-29 (Thu, 29 Apr 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp
    M llvm/test/CodeGen/AArch64/sve-coalesce-ptrue-intrinsics.ll
    R llvm/test/CodeGen/AArch64/sve-intrinsic-opts-reinterpret.ll
    A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-reinterpret.ll

  Log Message:
  -----------
  [AArch64][SVE] Move convert.{from,to}.svbool optimization into InstCombine

As part of this the ptrue coalescing done in SVEIntrinsicOpts has been
modified to not introduce redundant converts, since the convert removal
will no longer run after that optimisation to clean up.

Differential Revision: https://reviews.llvm.org/D101302


  Commit: 89085bcc86d4dad5cac1601f3c54b776e53eeaa4
      https://github.com/llvm/llvm-project/commit/89085bcc86d4dad5cac1601f3c54b776e53eeaa4
  Author: Bradley Smith <bradley.smith at arm.com>
  Date:   2021-04-29 (Thu, 29 Apr 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-dup.ll

  Log Message:
  -----------
  [AArch64][SVE] Convert svdup(vec, SV_VL1, elm) to insertelement(vec, elm, 0)

By converting the SVE intrinsic to a normal LLVM insertelement we give
the code generator a better chance to remove transitions between GPRs
and VPRs

Co-authored-by: Paul Walker <paul.walker at arm.com>

Depends on D101302

Differential Revision: https://reviews.llvm.org/D101167


  Commit: 354604a2a7149b5efd52134efa4765cf8c32e386
      https://github.com/llvm/llvm-project/commit/354604a2a7149b5efd52134efa4765cf8c32e386
  Author: Bradley Smith <bradley.smith at arm.com>
  Date:   2021-04-29 (Thu, 29 Apr 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    A llvm/test/CodeGen/AArch64/sve-insr.ll

  Log Message:
  -----------
  [AArch64][SVE] Use SIMD variant of INSR when scalar is the result of a vector extract

At the intrinsic layer the sve.insr operation takes a scalar. When this
scalar is an integer we are forcing a data transition between GPRs and
ZPRs that is potentially costly.

Often the integer scalar is the result of a vector extract, when
performing a reduction for example. In such cases we should keep all
data within the ZPRs.

Co-authored-by: Paul Walker <paul.walker at arm.com>

Differential Revision: https://reviews.llvm.org/D101169


Compare: https://github.com/llvm/llvm-project/compare/6841e6afba00...354604a2a714