[all-commits] [llvm/llvm-project] cea97f: GlobalISel: Relax verification of physical registe...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cea97fc0fcd86d52f9efa215116356b72faeb17d
      https://github.com/llvm/llvm-project/commit/cea97fc0fcd86d52f9efa215116356b72faeb17d
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-04-28 (Wed, 28 Apr 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/CodeGen/TargetRegisterInfo.cpp
    A llvm/test/MachineVerifier/test_copy_physregs_x86.mir

  Log Message:
  -----------
  GlobalISel: Relax verification of physical register copy types

This was picking a concrete size for a physical register, and
enforcing exact match on the virtual register's type size. Some
targets add multiple types to a register class, and some are smaller
than the full bit width. For example x86 adds f32 to 128-bit xmm
registers, and AMDGPU adds i16/f16 to 32-bit registers.

It might be better to represent these cases as a copy of the full
register and an extraction of the subpart, but a lot of code assumes
you can directly copy. This will help fix the current usage of the DAG
calling convention infrastructure which is incompatible with how
GlobalISel is now using it.

The API is somewhat cumbersome here, but I just mirrored the existing
functions, except now with LLTs (and allow returning null on failure,
unlike the MVT version). I think the concept of selecting register
classes based on type is flawed to begin with, but I'm trying to keep
this compatible with the existing handling.