[all-commits] [llvm/llvm-project] e05fda: [TableGen] Add predicate checks to isel patterns f...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e05fdab1250c0956ef9fc87fe764c9f0c144304d
      https://github.com/llvm/llvm-project/commit/e05fdab1250c0956ef9fc87fe764c9f0c144304d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-27 (Tue, 27 Apr 2021)

  Changed paths:
    M llvm/utils/TableGen/CodeGenDAGPatterns.cpp

  Log Message:
  -----------
  [TableGen] Add predicate checks to isel patterns for default HwMode.

As discussed in D100691 and based on D100889.

I removed the ModeChecks cache which provides little value. Reduced
from three loops to two. Used ArrayRef to pass the Predicate to
AppendPattern to avoid needing to construct a vector for single
mode. Used SmallVector to avoid heap allocation constructing
DefaultCheck for the in tree targets the use it.

Reviewed By: kparzysz

Differential Revision: https://reviews.llvm.org/D101240