[all-commits] [llvm/llvm-project] 262a72: [RISCV] Use stack slot to handle SPLAT_VECTOR_PART...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 262a72f50f1887591558ce0f521a5f7d3a17e2c2
      https://github.com/llvm/llvm-project/commit/262a72f50f1887591558ce0f521a5f7d3a17e2c2
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-26 (Mon, 26 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll

  Log Message:
  -----------
  [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32.

Reduces the amount of vector ALU operations and reduces vector
register pressure.