[all-commits] [llvm/llvm-project] caf129: [AMDGPU] Experiments show that the GCNRegBankReass...

[bsaleil via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: caf1294d95785503a1d114c8c167e181fff7068b
      https://github.com/llvm/llvm-project/commit/caf1294d95785503a1d114c8c167e181fff7068b
  Author: Baptiste Saleil <baptiste.saleil at amd.com>
  Date:   2021-04-26 (Mon, 26 Apr 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPU.h
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/lib/Target/AMDGPU/CMakeLists.txt
    R llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
    M llvm/test/CodeGen/AMDGPU/ctlz.ll
    M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fold-legalize-dag-increase-insts.ll
    M llvm/test/CodeGen/AMDGPU/frem.ll
    M llvm/test/CodeGen/AMDGPU/fshr.ll
    M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
    M llvm/test/CodeGen/AMDGPU/idot2.ll
    M llvm/test/CodeGen/AMDGPU/idot4s.ll
    M llvm/test/CodeGen/AMDGPU/idot4u.ll
    M llvm/test/CodeGen/AMDGPU/idot8s.ll
    M llvm/test/CodeGen/AMDGPU/idot8u.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll
    M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
    M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/memory_clause.ll
    R llvm/test/CodeGen/AMDGPU/regbank-reassign-split.mir
    R llvm/test/CodeGen/AMDGPU/regbank-reassign-wave64.mir
    R llvm/test/CodeGen/AMDGPU/regbank-reassign.mir
    M llvm/test/CodeGen/AMDGPU/saddo.ll
    M llvm/test/CodeGen/AMDGPU/saddsat.ll
    M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/store-local.128.ll
    M llvm/test/CodeGen/AMDGPU/store-local.96.ll
    M llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll
    M llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
    M llvm/test/CodeGen/AMDGPU/strict_fma.f64.ll
    M llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll
    M llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
    M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll

  Log Message:
  -----------
  [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
the compilation time and there is no case for which we see any improvement in
performance. This patch removes this pass and its associated test cases from
the tree.

Differential Revision: https://reviews.llvm.org/D101313

Change-Id: I0599169a7609c19a887f8d847a71e664030cc141