[all-commits] [llvm/llvm-project] e2cd92: [RISCV] Match splatted load to scalar load + splat...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e2cd92cb9bc2d71ff6fe0299583e48b38c1c6b97
      https://github.com/llvm/llvm-project/commit/e2cd92cb9bc2d71ff6fe0299583e48b38c1c6b97
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-26 (Mon, 26 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

  Log Message:
  -----------
  [RISCV] Match splatted load to scalar load + splat. Form strided load during isel.

This modifies my previous patch to push the strided load formation
to isel. This gives us opportunity to fold the splat into a .vx
operation first. Using a scalar register and a .vx operation reduces
vector register pressure which can be important for larger LMULs.

If we can't fold the splat into a .vx operation, then it can make
sense to use a strided load to free up the vector arithmetic
ALU to do actual arithmetic rather than tying it up with vmv.v.x.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D101138