[all-commits] [llvm/llvm-project] 1656df: [RISCV] Share RVInstIShift and RVInstIShiftW instr...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1656df13daa146afeb75ad832c94830a1f47d9cf
      https://github.com/llvm/llvm-project/commit/1656df13daa146afeb75ad832c94830a1f47d9cf
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-15 (Thu, 15 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td

  Log Message:
  -----------
  [RISCV] Share RVInstIShift and RVInstIShiftW instruction format classes with the B extension.

This generalizes RVInstIShift/RVInstIShiftW to take the upper
5 or 7 bits of the immediate as an input instead of only bit 30. Then
we can share them.

For RVInstIShift I left a hardcoded 0 at bit 26 where RV128 gets
a 7th bit for the shift amount.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D100424