[all-commits] [llvm/llvm-project] d5e962: [RISCV] Implement COPY for Zvlsseg registers

[ShihPo Hung via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d5e962f1f20c3e441b36785c572432000c80a728
      https://github.com/llvm/llvm-project/commit/d5e962f1f20c3e441b36785c572432000c80a728
  Author: ShihPo Hung <shihpo.hung at sifive.com>
  Date:   2021-04-13 (Tue, 13 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    A llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir

  Log Message:
  -----------
  [RISCV] Implement COPY for Zvlsseg registers

When copying Zvlsseg register tuples, we split the COPY to NF whole register moves
as below:

  $v10m2_v12m2 = COPY $v4m2_v6m2 # NF = 2
=>
  $v10m2 = PseudoVMV2R_V $v4m2
  $v12m2 = PseudoVMV2R_V $v6m2

This patch copies forwardCopyWillClobberTuple from AArch64 to check
register overlapping.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D100280