[all-commits] [llvm/llvm-project] 0148bf: [PowerPC] Use correct node to get a super register...

[Nemanja Ivanovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0148bf53f0a0b533eb742a7c8005a40328c48d66
      https://github.com/llvm/llvm-project/commit/0148bf53f0a0b533eb742a7c8005a40328c48d66
  Author: Nemanja Ivanovic <nemanja.i.ibm at gmail.com>
  Date:   2021-04-13 (Tue, 13 Apr 2021)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCInstrVSX.td
    M llvm/test/CodeGen/PowerPC/fp-strict-round.ll
    M llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll
    M llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
    M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

  Log Message:
  -----------
  [PowerPC] Use correct node to get a super register from a subreg

The VSX tablegen file has some rather eggregious uses of
COPY_TO_REGCLASS even in situations where it needs to use
SUBREG_TO_REG. While this produces correct code, it often doesn't
allow the register coalescer to coalesce copies and the resulting
code ends up being suboptimal. This patch just changes over
patterns that should use SUBREG_TO_REG.