[all-commits] [llvm/llvm-project] d737c4: [RISCV] Support vector SET[U]LT and SET[U]GE with ...

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d737c47137368ffe8e2c2ccee94a992f04369bed
      https://github.com/llvm/llvm-project/commit/d737c47137368ffe8e2c2ccee94a992f04369bed
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2021-04-12 (Mon, 12 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
    M llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll

  Log Message:
  -----------
  [RISCV] Support vector SET[U]LT and SET[U]GE with splatted immediates

This patch adds more optimized codegen for the above SETCC forms,
by matching the '.vi' vector forms when the immediate is a 5-bit signed
immediate plus 1. The immediate can be decremented and the corresponding
SET[U]LE or SET[U]GT forms can be matched.

This work was left as a TODO from D94168.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D100096