[all-commits] [llvm/llvm-project] ff9020: [RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ff902080a9fbf16fdeb076d3aadc8df6eea1cc04
      https://github.com/llvm/llvm-project/commit/ff902080a9fbf16fdeb076d3aadc8df6eea1cc04
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-11 (Sun, 11 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/alu16.ll
    M llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/div.ll
    M llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll

  Log Message:
  -----------
  [RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.

We don't need the sign extending behavior here and SLLI/SRLI
are able to compress to C.SLLI/C.SRLI.