[all-commits] [llvm/llvm-project] 48d69e: [RISCV] Add i8 and i16 srli and srai tests to Zbb/...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 48d69edadef1e4155106b183cd7219a1086454fe
      https://github.com/llvm/llvm-project/commit/48d69edadef1e4155106b183cd7219a1086454fe
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-11 (Sun, 11 Apr 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
    M llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll

  Log Message:
  -----------
  [RISCV] Add i8 and i16 srli and srai tests to Zbb/Zbp test files. NFC

These require the input to be zero or sign extended. If we have
sext.b, sext.h or zext.h instructions we can use them. Otherwise
we need to use a pair of shifts to accomplish the zero/sign extend
and the final shift.

We don't currently use zext.h when it is available.


  Commit: bc0e0527305d41bc55b27c60581749cb3ebdd5af
      https://github.com/llvm/llvm-project/commit/bc0e0527305d41bc55b27c60581749cb3ebdd5af
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-11 (Sun, 11 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
    M llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll

  Log Message:
  -----------
  [RISCV] Teach targetShrinkDemandedConstant to preserve (and X, 0xffff) when zext.h is supported.

Similar to what we do for zext.w.

Disable the (srl (and X, 0xffff), C) custom isel when zext.h is
available.


Compare: https://github.com/llvm/llvm-project/compare/91248e2db93a...bc0e0527305d