[all-commits] [llvm/llvm-project] cb1028: [RISCV] When custom iseling masked stores, copy th...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cb1028a0b95f5f4dd3924d81e8f8d9198b597ff4
      https://github.com/llvm/llvm-project/commit/cb1028a0b95f5f4dd3924d81e8f8d9198b597ff4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-05 (Mon, 05 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll

  Log Message:
  -----------
  [RISCV] When custom iseling masked stores, copy the mask into V0 instead of virtual register.

I missed a few intrinsics in 3dd4aa7d09599507d1f801ffe4bec4c9eebbb8da
when I did this for masked loads and masked segment loads/stores.

Found while trying to share more code between these custom isel
functions.