[all-commits] [llvm/llvm-project] af2837: [RISCV] Split RISCVISD::VMV_S_XF_VL into separate ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: af2837675a707fe7b2c1012038567ba1411045c5
      https://github.com/llvm/llvm-project/commit/af2837675a707fe7b2c1012038567ba1411045c5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-05 (Mon, 05 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

  Log Message:
  -----------
  [RISCV] Split RISCVISD::VMV_S_XF_VL into separate integer and FP.

It's a bit silly, but it allows us to write stricter type
constraints for isel. There's still some extra type checks in
the generated table due to some type interference limitations
around HWMode.


  Commit: 780a47285a7839faa8cfa6b670e96371e083011c
      https://github.com/llvm/llvm-project/commit/780a47285a7839faa8cfa6b670e96371e083011c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-05 (Mon, 05 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

  Log Message:
  -----------
  [RISCV] Add SDTCisInt to the SDTRVVSlide1 since it is only used for vslide1up.vx/vslide1down.vx.

The scalar type is already marked as XLenVT. The floating point
version would need a different rule.


Compare: https://github.com/llvm/llvm-project/compare/1d4c7429a72c...780a47285a78