[all-commits] [llvm/llvm-project] f6790b: [RISCV] Add missing CHECK-EXPAND line to one case ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f6790bec5c228476bc844648780a95f999707e3e
      https://github.com/llvm/llvm-project/commit/f6790bec5c228476bc844648780a95f999707e3e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-02 (Fri, 02 Apr 2021)

  Changed paths:
    M llvm/test/MC/RISCV/rv64i-aliases-valid.s

  Log Message:
  -----------
  [RISCV] Add missing CHECK-EXPAND line to one case in rv64i-aliases-valid.s.

Use -NEXT to protect against other missing lines.


  Commit: d7ffa82a8e621ce9a19b98c922adc53d6b7cd9f3
      https://github.com/llvm/llvm-project/commit/d7ffa82a8e621ce9a19b98c922adc53d6b7cd9f3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-02 (Fri, 02 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
    M llvm/test/CodeGen/RISCV/calling-conv-half.ll
    M llvm/test/CodeGen/RISCV/imm.ll
    M llvm/test/MC/RISCV/rv64i-aliases-valid.s

  Log Message:
  -----------
  [RISCV] Improve 64-bit integer constant materialization for more cases.

For positive constants we try shifting left to remove leading zeros
and fill the bottom bits with 1s. We then materialize that constant
shift it right.

This patch adds a new strategy to try filling the bottom bits with
zeros instead. This catches some additional cases.


Compare: https://github.com/llvm/llvm-project/compare/412fc74140c0...d7ffa82a8e62