[all-commits] [llvm/llvm-project] 5a9a8c: [RISCV] Add more nxvi64 vector intrinsic tests for...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5a9a8c7cd4179bb2ea4fa916719e270b97847f74
      https://github.com/llvm/llvm-project/commit/5a9a8c7cd4179bb2ea4fa916719e270b97847f74
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-01 (Thu, 01 Apr 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vse-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsse-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwredsum-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll

  Log Message:
  -----------
  [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC

This confirms we handle most instrutions gracefully. We do
currently fail for vslide1up and vslide1down though.