[all-commits] [llvm/llvm-project] 766d27: [RISCV] Add isel patterns to handle vrsub intrinsi...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 766d27dc857200cd1fbb3a30e62b84ce271fb84f
      https://github.com/llvm/llvm-project/commit/766d27dc857200cd1fbb3a30e62b84ce271fb84f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-01 (Thu, 01 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll

  Log Message:
  -----------
  [RISCV] Add isel patterns to handle vrsub intrinsic with 2 vector operands.

This occurs when we type legalize an i64 scalar input on RV32. We
need to manually splat, which requires a vector input. Rather
than special case this in lowering just pattern match it.