[all-commits] [llvm/llvm-project] d157e3: [RISCV] Fix handling of nxvXi64 vmsgt(u).vx intrin...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d157e3f387c918a6736fb29fccd78a80425e5f88
      https://github.com/llvm/llvm-project/commit/d157e3f387c918a6736fb29fccd78a80425e5f88
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-04-01 (Thu, 01 Apr 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll

  Log Message:
  -----------
  [RISCV] Fix handling of nxvXi64 vmsgt(u).vx intrinsics on RV32.

We need to splat the scalar separately and use .vv, but there is
no vmsgt(u).vv. So add isel patterns to select vmslt(u).vv with
swapped operands.

We also need to get VT to use for the splat from an operand rather
than the result since the result VT is nxvXi1.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D99704