[all-commits] [llvm/llvm-project] 2a8b7c: [RISCV] Add RISCVISD opcodes for CLZW and CTZW.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2a8b7cab6a3b52ab27acc44ba50a1528c8aa2d44
      https://github.com/llvm/llvm-project/commit/2a8b7cab6a3b52ab27acc44ba50a1528c8aa2d44
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-31 (Wed, 31 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv64zbb.ll

  Log Message:
  -----------
  [RISCV] Add RISCVISD opcodes for CLZW and CTZW.

Our CLZW isel pattern is quite easily broken by surrounding code
preventing it from matching sometimes. This usually results in
failing to remove the and X, 0xffffffff inserted by type
legalization. The add with -32 that type legalization also inserts
will often gets combined into other add/sub nodes. That doesn't
usually result in extra code when we don't use clzw.

CTTZ seems to be less fragile, but I wanted to keep it consistent
with CTLZ.

Reviewed By: asb, HsiangKai

Differential Revision: https://reviews.llvm.org/D99317