[all-commits] [llvm/llvm-project] 04f10a: [RISCV] Add isel patterns to select vsub_vx intrin...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 04f10ab367b5c547f5de3285890e74146a5949b0
      https://github.com/llvm/llvm-project/commit/04f10ab367b5c547f5de3285890e74146a5949b0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-31 (Wed, 31 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll

  Log Message:
  -----------
  [RISCV] Add isel patterns to select vsub_vx intrinsic to vadd.vi if it uses a small enough immediate

Also modify the simm5_plus1 check because Imm-1 is UB if Imm happens
to be INT64_MIN. I don't think the compiler would optimize based on that in this
usage, but it could fail UBSan or -ftrapv.

Reviewed By: HsiangKai, frasercrmck

Differential Revision: https://reviews.llvm.org/D99637