[all-commits] [llvm/llvm-project] 700431: [GlobalISel][AArch64] Combine G_SEXT_INREG + right...

[Jessica Paquette via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 700431128e212d5ef53afb6d20da098ca264cadd
      https://github.com/llvm/llvm-project/commit/700431128e212d5ef53afb6d20da098ca264cadd
  Author: Jessica Paquette <jpaquette at apple.com>
  Date:   2021-03-30 (Tue, 30 Mar 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/Target/AArch64/AArch64Combine.td
    M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
    A llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-sextinreg.mir

  Log Message:
  -----------
  [GlobalISel][AArch64] Combine G_SEXT_INREG + right shift -> G_SBFX

Basically a port of isBitfieldExtractOpFromSExtInReg in AArch64ISelDAGToDAG.

This is only done post-legalization for now. Once the legalizer knows how to
decompose these back into shifts, this requirement can probably be removed.

Differential Revision: https://reviews.llvm.org/D99230