[all-commits] [llvm/llvm-project] 5821a5: [RISCV] Add inline asm constraint 'vr' and 'vm' in...

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5821a58d8e4c5510a4ab30fa758a9d22f41c346a
      https://github.com/llvm/llvm-project/commit/5821a58d8e4c5510a4ab30fa758a9d22f41c346a
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-03-30 (Tue, 30 Mar 2021)

  Changed paths:
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/lib/Basic/Targets/RISCV.h
    A clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c

  Log Message:
  -----------
  [RISCV] Add inline asm constraint 'vr' and 'vm' in Clang for RISC-V 'V'.

Add asm constraint 'vr' for vector registers.
Add asm constraint 'vm' for vector mask registers.

Differential Revision: https://reviews.llvm.org/D98616