[all-commits] [llvm/llvm-project] 9745dc: [SelectionDAG][AArch64][SVE] Perform SETCC conditi...

[Bradley Smith via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9745dce8c3dc6996dae9bab11ff410a12d8daec7
      https://github.com/llvm/llvm-project/commit/9745dce8c3dc6996dae9bab11ff410a12d8daec7
  Author: Bradley Smith <bradley.smith at arm.com>
  Date:   2021-03-29 (Mon, 29 Mar 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    A llvm/test/CodeGen/AArch64/sve-fixed-length-float-compares.ll
    M llvm/test/CodeGen/PowerPC/vsx.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll

  Log Message:
  -----------
  [SelectionDAG][AArch64][SVE] Perform SETCC condition legalization in LegalizeVectorOps

This is currently performed in SelectionDAGLegalize, here we make it also
happen in LegalizeVectorOps, allowing a target to lower the SETCC condition
codes first in LegalizeVectorOps and then lower to a custom node afterwards,
without having to duplicate all of the SETCC condition legalization in the
target specific lowering.

As a result of this, fixed length floating point SETCC nodes can now be
properly lowered for SVE.

Differential Revision: https://reviews.llvm.org/D98939