[all-commits] [llvm/llvm-project] 5692fc: [RISCV] Add a pattern for (sext_inreg (mul (and X, ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5692fc38e0d17abc55a4a84da98f021a1d53d76d
      https://github.com/llvm/llvm-project/commit/5692fc38e0d17abc55a4a84da98f021a1d53d76d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-27 (Sat, 27 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoM.td
    M llvm/test/CodeGen/RISCV/xaluo.ll

  Log Message:
  -----------
  [RISCV] Add a pattern for (sext_inreg (mul (and X, 0xffffffff), (and Y, 0xffffffff)), i32) to suppress MULW formation

We have a special pattern for
(mul (and X, 0xffffffff), (and Y, 0xffffffff)), to optimize the
ANDs to shift. But if a sext_inreg coms first, we'll form a MULW
and limit the effectiveness of the special match. So this patch
adds a larger pattern to suppress the MULW formation by emitting
a sext.w and then the same output we use for the
(mul (and X, 0xffffffff), (and Y, 0xffffffff)). This should all
get CSEd.

This is the issue I was trying to fix with D99029, but that affected
many more tests.