[all-commits] [llvm/llvm-project] 4d5ee7: [RISCV] Merge FMulAdd and FMulSub scheduler classe...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4d5ee71b52657ef8871a34d91fe41f8a339e96f3
      https://github.com/llvm/llvm-project/commit/4d5ee71b52657ef8871a34d91fe41f8a339e96f3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-26 (Fri, 26 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedule.td

  Log Message:
  -----------
  [RISCV] Merge FMulAdd and FMulSub scheduler classes to a single FMA scheduler class. NFC

It's unlikely that FMADD and FMSUB would have different scheduling
information so merge them.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D99140