[all-commits] [llvm/llvm-project] c41f2f: [RISCV] Add scheduler classes for the Zba and Zbb ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c41f2f6492824b15c1fbf6a6f64f168b9c5621c0
      https://github.com/llvm/llvm-project/commit/c41f2f6492824b15c1fbf6a6f64f168b9c5621c0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-26 (Fri, 26 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedule.td

  Log Message:
  -----------
  [RISCV] Add scheduler classes for the Zba and Zbb extensions.

I've used IALU for the simplest operations from Zbb:
min, minu, max, maxu, sext.b, sext.h, zext.h, andn, orn, xnor

I've put add.uw in IALU32 and slli.uw in ShiftImm32.

Remaining instructions have received new classes.
All 3 sh*add are grouped together. sh*add.uw are grouped together.
Rotate left and right are together. Everything else got their own
class containing one instruction.

I think what I have here is the minimum granularity we need. I
could be convinced that we need more classes.

Reviewed By: evandro

Differential Revision: https://reviews.llvm.org/D99040