[all-commits] [llvm/llvm-project] 9049cf: [RISCV] Add constraint for RVV indexed loads.

[Zakk Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9049cf77e39443b479b5c8f56f88b93c698c7876
      https://github.com/llvm/llvm-project/commit/9049cf77e39443b479b5c8f56f88b93c698c7876
  Author: Zakk Chen <zakk.chen at sifive.com>
  Date:   2021-03-26 (Fri, 26 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll

  Log Message:
  -----------
  [RISCV] Add constraint for RVV indexed loads.

Add the constraint when destination EEW not equals the source EEW for
correctness.

The RVV spec has three register overlap rules and I implement the first
stricter constraint because the others are difficult to enforce.

Reviewed By: frasercrmck, craig.topper

Differential Revision: https://reviews.llvm.org/D98920