[all-commits] [llvm/llvm-project] 8f62a8: [RISCV] Optimize (and (shl GPR:, uimm5:), 0xffffff...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8f62a80328e34aee34246af4d7e3981ebe9ef37f
      https://github.com/llvm/llvm-project/commit/8f62a80328e34aee34246af4d7e3981ebe9ef37f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-25 (Thu, 25 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll

  Log Message:
  -----------
  [RISCV] Optimize (and (shl GPR:, uimm5:), 0xffffffff) to use 2 shifts instead of 3.

The and would normally become SLLI+SRLI, giving us 2 SLLI+SRLI. We
can detect this and combine the 2 SLLIs into 1.