[all-commits] [llvm/llvm-project] 55d18b: [TTI] Return a TypeSize from getRegisterBitWidth.

[sdesmalen-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 55d18b3cc236f13e67e22cb8c1f13f92c10306c0
      https://github.com/llvm/llvm-project/commit/55d18b3cc236f13e67e22cb8c1f13f92c10306c0
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2021-03-24 (Wed, 24 Mar 2021)

  Changed paths:
    M llvm/include/llvm/Analysis/TargetTransformInfo.h
    M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
    M llvm/include/llvm/CodeGen/BasicTTIImpl.h
    M llvm/lib/Analysis/TargetTransformInfo.cpp
    M llvm/lib/CodeGen/TypePromotion.cpp
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
    M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
    M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
    M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
    M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
    M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
    M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
    M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
    M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
    M llvm/lib/Target/VE/VETargetTransformInfo.h
    M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
    M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
    M llvm/lib/Target/X86/X86TargetTransformInfo.h
    M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

  Log Message:
  -----------
  [TTI] Return a TypeSize from getRegisterBitWidth.

This patch changes the interface to take a RegisterKind, to indicate
whether the register bitwidth of a scalar register, fixed-width vector
register, or scalable vector register must be returned.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D98874