[all-commits] [llvm/llvm-project] 8db480: [RISCV] Remove unused SchedWrites WriteFConv32/Wri...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8db4804da710ef2c83c76f5753dfa4f0b2aaa6ee
      https://github.com/llvm/llvm-project/commit/8db4804da710ef2c83c76f5753dfa4f0b2aaa6ee
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-22 (Mon, 22 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedule.td

  Log Message:
  -----------
  [RISCV] Remove unused SchedWrites WriteFConv32/WriteFConv64/WriteFMov32/WriteFMov64.

It doesn't look like any instructions have ever been assigned to these classes.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D99050


  Commit: d7b0c19823892b2c94a9e347dec880a3531980ff
      https://github.com/llvm/llvm-project/commit/d7b0c19823892b2c94a9e347dec880a3531980ff
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-22 (Mon, 22 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedule.td

  Log Message:
  -----------
  [RISCV] Add scheduler classes to Zfh instructions.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D99053


Compare: https://github.com/llvm/llvm-project/compare/b5e96e0ad601...d7b0c1982389