[all-commits] [llvm/llvm-project] a81dff: [RISCV] Support inline asm for vector instructions.

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a81dff1e58390ccd438b9d5ffeb289783f2ccd29
      https://github.com/llvm/llvm-project/commit/a81dff1e58390ccd438b9d5ffeb289783f2ccd29
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-03-15 (Mon, 15 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    A llvm/test/CodeGen/RISCV/rvv/inline-asm.ll

  Log Message:
  -----------
  [RISCV] Support inline asm for vector instructions.

Types of fractional LMUL and LMUL=1 are all using VR register class. When
using inline asm, it will use the first type in the register class as the
type for the register. It is not necessary the same as the value type. We
need to use INSERT_SUBVECTOR/EXTRACT_SUBVECToR/BITCAST to make it legal
to put the value in the corresponding register class.

Differential Revision: https://reviews.llvm.org/D97480