[all-commits] [llvm/llvm-project] 5b8254: [DAGCombiner] Optimize 1-bit smulo to AND+SETNE.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5b825433d7854f2e79966606ddfb381806cc499c
      https://github.com/llvm/llvm-project/commit/5b825433d7854f2e79966606ddfb381806cc499c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-13 (Sat, 13 Mar 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/vec_smulo.ll

  Log Message:
  -----------
  [DAGCombiner] Optimize 1-bit smulo to AND+SETNE.

A 1-bit smulo overflows is both inputs are -1 since the result
should be +1 which can't be represented in a signed 1 bit value.

We can detect this with an AND and a setcc. The multiply result
can also use the same AND.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D97634