[all-commits] [llvm/llvm-project] 3231d2: AMDGPU/GlobalISel: Cleanup call lowering sequence

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3231d2b581f57ae1587587e436bc2873ce1470ce
      https://github.com/llvm/llvm-project/commit/3231d2b581f57ae1587587e436bc2873ce1470ce
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

  Log Message:
  -----------
  AMDGPU/GlobalISel: Cleanup call lowering sequence

Now that handleAssignments is handling all of the argument splitting,
we don't have to move the insert point around.


  Commit: d44a3dad994bac112850e929e36f97e6963cd481
      https://github.com/llvm/llvm-project/commit/d44a3dad994bac112850e929e36f97e6963cd481
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll

  Log Message:
  -----------
  AArch64/GlobalISel: Don't use common prefix in test

Unlike update_llc_test_checks, update_mir_test_checks isn't actually
smart enough to common functions with identical output.


  Commit: 34471c30602b5deccca4ed7607721e819e26b39c
      https://github.com/llvm/llvm-project/commit/34471c30602b5deccca4ed7607721e819e26b39c
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll

  Log Message:
  -----------
  GlobalISel: Partially fix handling of byval arguments

This was essentially ignoring byval and treating them as a pointer
argument which needed to be loaded from. This should copy the frame
index value to the virtual register, not insert a load from the frame
index into the pointer value.

For AMDGPU, this was producing a load from the byval pointer argument,
to a pointer used for the byval arguments. I do not understand how
AArch64 managed to work before since it appears to be similarly
broken.

We could also change the ValueHandler API to avoid the extra copy from
the frame index, since currently it returns a new register.

I believe there is still an issue with outgoing byval arguments. These
should have a copy inserted in case the callee decided to overwrite
the memory.


  Commit: 6b76d82853fdc64160dda44610407c04af620292
      https://github.com/llvm/llvm-project/commit/6b76d82853fdc64160dda44610407c04af620292
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
    M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
    M llvm/lib/Target/ARM/ARMCallLowering.cpp
    M llvm/lib/Target/Mips/MipsCallLowering.cpp
    M llvm/lib/Target/X86/X86CallLowering.cpp
    A llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-objects.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll

  Log Message:
  -----------
  GlobalISel: Fix marking byval arguments as immutable

byval arguments need to be assumed writable. Only implicitly stack
passed arguments which aren't addressable in the IR can be assumed
immutable.

Mips is still broken since for some reason its doing its own thing
with the ValueHandlers (and x86 doesn't actually handle byval
arguments now, although some of the code is there).


Compare: https://github.com/llvm/llvm-project/compare/bc4a5bdce4af...6b76d82853fd