[all-commits] [llvm/llvm-project] 641f57: [RISCV] Optimize INSERT_VECTOR_ELT sequences

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 641f5700f9404e2b13fca0c3620d60e795222045
      https://github.com/llvm/llvm-project/commit/641f5700f9404e2b13fca0c3620d60e795222045
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll

  Log Message:
  -----------
  [RISCV] Optimize INSERT_VECTOR_ELT sequences

This patch optimizes the codegen for INSERT_VECTOR_ELT in various ways.
Primarily, it removes the use of vslidedown during lowering, and the
vector element is inserted entirely using vslideup with a custom VL and
slide index.

Additionally, lowering of i64-element vectors on RV32 has been optimized
in several ways. When the 64-bit value to insert is the same as the
sign-extension of the lower 32-bits, the codegen can follow the regular
path. When this is not possible, a new sequence of two i32 vslide1up
instructions is used to get the vector element into a vector. This
sequence was suggested by @craig.topper. From there, the value is slid
into the final position for more consistent lowering across RV32 and
RV64.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D98250