[all-commits] [llvm/llvm-project] 1a8082: [AArch64] Extend vecreduce -> udot handling to mla...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1a808286eff01fde07794b2c94138a96e7099561
      https://github.com/llvm/llvm-project/commit/1a808286eff01fde07794b2c94138a96e7099561
  Author: David Green <david.green at arm.com>
  Date:   2021-03-10 (Wed, 10 Mar 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/neon-dotreduce.ll

  Log Message:
  -----------
  [AArch64] Extend vecreduce -> udot handling to mla reductions

We previously have lowering for:
  vecreduce.add(zext(X)) to vecreduce.add(UDOT(zero, X, one))
This extends that to also handle:
  vecreduce.add(mul(zext(X), zext(Y)) to vecreduce.add(UDOT(zero, X, Y))
It extends the existing code to optionally handle a mul with equal
extends.

Differential Revision: https://reviews.llvm.org/D97280