[all-commits] [llvm/llvm-project] 1e3911: [RISCV] Manually split vector operands to VECREDUC...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1e39118638cd77c416f2456828bc2b90b8f194ad
      https://github.com/llvm/llvm-project/commit/1e39118638cd77c416f2456828bc2b90b8f194ad
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-10 (Wed, 10 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

  Log Message:
  -----------
  [RISCV] Manually split vector operands to VECREDUCE when handling vXi64 vectors on RV32.

The type legalizer will visit the result before the operands. To
avoid creating an illegal target specific node or falling back to
scalarization, we need to manually split vector operands.

This still doesn't handle the case of non-power of 2 operands
which need to be widened. I'm not sure the type legalizer is
ready for it. I think we would need to insert an
INSERT_SUBVECTOR with the power of 2 type we want, with an undef
first operand, and the non-power of 2 orignal operand as the vector
to insert. Then fill in the neutral elements into the elements the
padded elements. Alternatively we INSERT_SUBVECTOR into a neutral vector.
>From there we carry on splitting if needed to get to a legal type
then do the target specific code.

The problem with this is the type legalizer doesn't know how to
widen an insert_subvector yet. We would need to add that including
the handling for a non-undef first vector.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D98292