[all-commits] [llvm/llvm-project] 4c6ab4: GlobalISel: Try to combine G_[SU]DIV and G_[SU]REM

[Christudasan Devadasan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4c6ab48fb1149c4f1f1d2953f5d232211b3a6bce
      https://github.com/llvm/llvm-project/commit/4c6ab48fb1149c4f1f1d2953f5d232211b3a6bce
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2021-03-10 (Wed, 10 Mar 2021)

  Changed paths:
    M llvm/docs/GlobalISel/GenericOpcode.rst
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
    M llvm/include/llvm/Support/TargetOpcodes.def
    M llvm/include/llvm/Target/GenericOpcodes.td
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-divrem.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir
    M llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

  Log Message:
  -----------
  GlobalISel: Try to combine G_[SU]DIV and G_[SU]REM

It is good to have a combined `divrem` instruction when the
`div` and `rem` are computed from identical input operands.
Some targets can lower them through a single expansion that
computes both division and remainder. It effectively reduces
the number of instructions than individually expanding them.

Reviewed By: arsenm, paquette

Differential Revision: https://reviews.llvm.org/D96013