[all-commits] [llvm/llvm-project] 5cdb2e: [RISCV][MC] Fix nf encoding for vector ld/st whole...

[ShihPo Hung via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5cdb2e98608bf57c216ee7067e8a12d070c9e2bd
      https://github.com/llvm/llvm-project/commit/5cdb2e98608bf57c216ee7067e8a12d070c9e2bd
  Author: ShihPo Hung <shihpo.hung at sifive.com>
  Date:   2021-03-08 (Mon, 08 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/test/MC/RISCV/rvv/aliases.s
    M llvm/test/MC/RISCV/rvv/load.s
    M llvm/test/MC/RISCV/rvv/store.s

  Log Message:
  -----------
  [RISCV][MC] Fix nf encoding for vector ld/st whole register

The three bit nf is one less than the number of NFIELDS,
so we manually decrement 1 for VS1/2/4/8R & VL1/2/4/8R.

Reviewed By: craig.topper

Differential revision: https://reviews.llvm.org/D98185