[all-commits] [llvm/llvm-project] a26512: [RISCV] Add explicit i64 types to RV64 isel patter...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a2651266c5eb08f9dcb059247a35b1ce88ad148e
      https://github.com/llvm/llvm-project/commit/a2651266c5eb08f9dcb059247a35b1ce88ad148e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-08 (Mon, 08 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoM.td

  Log Message:
  -----------
  [RISCV] Add explicit i64 types to RV64 isel patterns to stop tablegen from generating unneeded i32 patterns for RV32 HwMode.