[all-commits] [llvm/llvm-project] b0f011: [AIX][TLS] Generate 32-bit general-dynamic access ...
Nemanja Ivanovic via All-commits
all-commits at lists.llvm.org
Mon Mar 8 07:31:21 PST 2021
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: b0f0115308e4e8692b254c3b0e20f3743616b2d5
https://github.com/llvm/llvm-project/commit/b0f0115308e4e8692b254c3b0e20f3743616b2d5
Author: Nemanja Ivanovic <nemanja.i.ibm at gmail.com>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
M llvm/lib/Target/PowerPC/PPCTargetStreamer.h
M llvm/test/CodeGen/PowerPC/aix-tls-checks.ll
A llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll
A llvm/test/CodeGen/PowerPC/aix-tls-gd-int.ll
A llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll
Log Message:
-----------
[AIX][TLS] Generate 32-bit general-dynamic access code sequence
Adds support for the TLS general dynamic access model to
assembly files on AIX 32-bit.
To generate the correct code sequence when accessing a TLS variable
`v`, we first create two TOC entry nodes, one for the variable offset, one
for the region handle. These nodes are followed by a `PPCISD::TLSGD_AIX`
node (new node introduced by this patch).
The `PPCISD::TLSGD_AIX` node (`TLSGDAIX` pseudo instruction) is
expanded to 2 copies (to put the variable offset and region handle in
the right registers) and a call to `__tls_get_addr`.
This patch also changes the way TC entries are generated in asm files.
If the generated TC entry is for the region handle of a TLS variable,
we add the `@m` relocation and the `.` prefix to the entry name.
For example:
```
L..C0:
.tc .v[TC],v[TL]@m -> region handle
L..C1:
.tc v[TC],v[TL] -> variable offset
```
Reviewed By: nemanjai, sfertile
Differential Revision: https://reviews.llvm.org/D97948
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