[all-commits] [llvm/llvm-project] 8725b2: [AArch64] Legalize horizontal fmax/fmin reductions...

[LemonBoy via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8725b24c6d4abaa97425e704652a13dacb35fe3f
      https://github.com/llvm/llvm-project/commit/8725b24c6d4abaa97425e704652a13dacb35fe3f
  Author: LemonBoy <thatlemon at gmail.com>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll

  Log Message:
  -----------
  [AArch64] Legalize horizontal fmax/fmin reductions on f16 vectors

Expand the horizontal reduction during the instruction selection phase, but only if the target doesn't support the full fp16 instruction set.

Fixes https://bugs.llvm.org/show_bug.cgi?id=49401

Reviewed By: aemerson

Differential Revision: https://reviews.llvm.org/D97840