[all-commits] [llvm/llvm-project] d28297: [RISCV] Enable fixed-length vectorization of LoopV...

[Luke via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d28297ff68eeecc381426416ff92a466953cd93d
      https://github.com/llvm/llvm-project/commit/d28297ff68eeecc381426416ff92a466953cd93d
  Author: Luke <luke957 at foxmail.com>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    A llvm/test/Transforms/LoopVectorize/RISCV/riscv-unroll.ll

  Log Message:
  -----------
  [RISCV] Enable fixed-length vectorization of LoopVectorizer for RISC-V Vector

By implementing the method "unsigned RISCVTTIImpl::getRegisterBitWidth(bool Vector)",
fixed-length vectorization is enabled when possible. Without this method, the
"#pragma clang loop" directive is needed to enable vectorization(or the cost model
may inform LLVM that "Vectorization is possible but not beneficial").

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D97549