[all-commits] [llvm/llvm-project] 4c8fb7: [GlobalISel] Start using vectors in GISelKnownBits

[petar-avramovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4c8fb7ddd6fa49258e0e9427e7345fb56ba522d4
      https://github.com/llvm/llvm-project/commit/4c8fb7ddd6fa49258e0e9427e7345fb56ba522d4
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-urem-pow-2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
    M llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt
    M llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
    A llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp

  Log Message:
  -----------
  [GlobalISel] Start using vectors in GISelKnownBits

For vectors we consider a bit as known if it is the same for all demanded
vector elements (all elements by default). KnownBits BitWidth for vector
type is size of vector element. Add support for G_BUILD_VECTOR.
This allows combines of urem_pow2_to_mask in pre-legalizer combiner.

Differential Revision: https://reviews.llvm.org/D96122


  Commit: 4112299ee761a9b6a309c8ff4a7e75f8c8d8851b
      https://github.com/llvm/llvm-project/commit/4112299ee761a9b6a309c8ff4a7e75f8c8d8851b
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-zext-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll

  Log Message:
  -----------
  [GlobalISel] Combine zext(trunc x) to x

Combine zext(trunc x) to x when truncated bits are known to be zero.

Differential Revision: https://reviews.llvm.org/D96031


  Commit: bf5a5826504754788a8f1e3fec7a7dc95cda5782
      https://github.com/llvm/llvm-project/commit/bf5a5826504754788a8f1e3fec7a7dc95cda5782
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCombine.td
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

  Log Message:
  -----------
  AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect

RegBankSelect creates zext and trunc when it selects banks for uniform i1.
Add zext_trunc_fold from generic combiner to post RegBankSelect combiner.

Differential Revision: https://reviews.llvm.org/D95432


Compare: https://github.com/llvm/llvm-project/compare/fe5c2c3ca682...bf5a58265047