[all-commits] [llvm/llvm-project] d79169: [MCA] Add support for in-order CPUs

[Andrew Savonichev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d791695cb5172b527e1b0717458d8852abcf34d1
      https://github.com/llvm/llvm-project/commit/d791695cb5172b527e1b0717458d8852abcf34d1
  Author: Andrew Savonichev <andrew.savonichev at gmail.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M llvm/docs/CommandGuide/llvm-mca.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/include/llvm/MC/MCSchedule.h
    M llvm/include/llvm/MCA/Context.h
    M llvm/include/llvm/MCA/HardwareUnits/RegisterFile.h
    M llvm/include/llvm/MCA/HardwareUnits/RetireControlUnit.h
    M llvm/include/llvm/MCA/Instruction.h
    A llvm/include/llvm/MCA/Stages/InOrderIssueStage.h
    M llvm/include/llvm/MCA/Stages/RetireStage.h
    M llvm/include/llvm/Target/TargetSchedule.td
    M llvm/lib/MCA/CMakeLists.txt
    M llvm/lib/MCA/Context.cpp
    M llvm/lib/MCA/HardwareUnits/RetireControlUnit.cpp
    M llvm/lib/MCA/InstrBuilder.cpp
    A llvm/lib/MCA/Stages/InOrderIssueStage.cpp
    M llvm/lib/MCA/Stages/RetireStage.cpp
    M llvm/lib/Target/AArch64/AArch64SchedA55.td
    M llvm/test/TableGen/InvalidMCSchedClassDesc.td
    A llvm/test/tools/llvm-mca/AArch64/Cortex/A55-add-sequence.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/A55-in-order-retire.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/A55-out-of-order-retire.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/in-order-bottleneck-analysis.s
    A llvm/test/tools/llvm-mca/ARM/m7-negative-readadvance.s
    M llvm/test/tools/llvm-mca/X86/in-order-cpu.s
    M llvm/tools/llvm-mca/llvm-mca.cpp
    M llvm/utils/TableGen/SubtargetEmitter.cpp

  Log Message:
  -----------
  [MCA] Add support for in-order CPUs

This patch adds a pipeline to support in-order CPUs such as ARM
Cortex-A55.

In-order pipeline implements a simplified version of Dispatch,
Scheduler and Execute stages as a single stage. Entry and Retire
stages are common for both in-order and out-of-order pipelines.

Differential Revision: https://reviews.llvm.org/D94928