[all-commits] [llvm/llvm-project] a968e7: [ARM] KnownBits for CSINC/CSNEG/CSINV
David Green via All-commits
all-commits at lists.llvm.org
Thu Mar 4 00:40:45 PST 2021
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: a968e7b82eac364d411c81aae58722a0b3a4b29c
https://github.com/llvm/llvm-project/commit/a968e7b82eac364d411c81aae58722a0b3a4b29c
Author: David Green <david.green at arm.com>
Date: 2021-03-04 (Thu, 04 Mar 2021)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
M llvm/test/CodeGen/Thumb2/active_lane_mask.ll
M llvm/test/CodeGen/Thumb2/mve-ctlz.ll
M llvm/test/CodeGen/Thumb2/mve-cttz.ll
M llvm/test/CodeGen/Thumb2/mve-fmas.ll
M llvm/test/CodeGen/Thumb2/mve-fmath.ll
M llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
M llvm/test/CodeGen/Thumb2/mve-masked-store.ll
M llvm/test/CodeGen/Thumb2/mve-nounrolledremainder.ll
M llvm/test/CodeGen/Thumb2/mve-pred-and.ll
M llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
M llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
M llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
M llvm/test/CodeGen/Thumb2/mve-pred-not.ll
M llvm/test/CodeGen/Thumb2/mve-pred-or.ll
M llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
M llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
M llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
M llvm/test/CodeGen/Thumb2/mve-selectcc.ll
M llvm/test/CodeGen/Thumb2/mve-vcmp.ll
M llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
M llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
M llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
M llvm/test/CodeGen/Thumb2/mve-vcmpr.ll
M llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
M llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
M llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
M llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
A llvm/unittests/Target/ARM/ARMSelectionDAGTest.cpp
M llvm/unittests/Target/ARM/CMakeLists.txt
Log Message:
-----------
[ARM] KnownBits for CSINC/CSNEG/CSINV
This adds some simple known bits handling for the three CSINC/NEG/INV
instructions. From the operands known bits we can compute the common
bits of the first operand and incremented/negated/inverted second
operand. The first, especially CSINC ZR, ZR, comes up fair amount in the
tests. The others are more rare so a unit test for them is added.
Differential Revision: https://reviews.llvm.org/D97788
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