[all-commits] [llvm/llvm-project] 438c98: [ARM] Use 0, not ZR during ISel for CSINC/INV/NEG

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 438c98515c23a111992d332e316824d0a17f2ea4
      https://github.com/llvm/llvm-project/commit/438c98515c23a111992d332e316824d0a17f2ea4
  Author: David Green <david.green at arm.com>
  Date:   2021-03-02 (Tue, 02 Mar 2021)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMInstrThumb2.td

  Log Message:
  -----------
  [ARM] Use 0, not ZR during ISel for CSINC/INV/NEG

Instead of converting the 0 into a ZR reg during lowering, do that with
tablegen by matching the zero immediate. This when combined with other
optimizations is more likely to use ZR and helps keep the DAG more
easily optimizable. It should not otherwise effect code generation.