[all-commits] [llvm/llvm-project] e745f7: [LegalizeTypes] Improve ExpandIntRes_XMULO codegen.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e745f7c563734bcc958d528714493ee79581d23a
      https://github.com/llvm/llvm-project/commit/e745f7c563734bcc958d528714493ee79581d23a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-03-01 (Mon, 01 Mar 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/AArch64/umulo-128-legalisation-lowering.ll
    M llvm/test/CodeGen/AArch64/vec_umulo.ll
    M llvm/test/CodeGen/PowerPC/pr45448.ll
    M llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
    M llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll

  Log Message:
  -----------
  [LegalizeTypes] Improve ExpandIntRes_XMULO codegen.

The code previously used two BUILD_PAIRs to concatenate the two UMULO
results with 0s in the lower bits to match original VT. Then it created
an ADD and a UADDO with the original bit width. Each of those operations
need to be expanded since they have illegal types.

Since we put 0s in the lower bits before the ADD, the lower half of the
ADD result will be 0. So the lower half of the UADDO result is
solely determined by the other operand. Since the UADDO need to
be split in half, we don't really needd an operation for the lower
bits. Unfortunately, we don't see that in type legalization and end up
creating something more complicated and DAG combine or
lowering aren't always able to recover it.

This patch directly generates the narrower ADD and UADDO to avoid
needing to legalize them. Now only the MUL is done on the original
type.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D97440