[all-commits] [llvm/llvm-project] 3bc5ed: [RISCV] Support fixed-length vector sign/zero exte...

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3bc5ed38750c6a6daff39ad524b75e40c8c09183
      https://github.com/llvm/llvm-project/commit/3bc5ed38750c6a6daff39ad524b75e40c8c09183
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2021-02-25 (Thu, 25 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll

  Log Message:
  -----------
  [RISCV] Support fixed-length vector sign/zero extension

This patch adds support for the custom lowering sign- and zero-extension
of fixed-length vector types. It does so through custom nodes. Since the
source and destination types are (necessarily) of different sizes, it is
possible that the source type is legal whilst the larger destination
type isn't. In this case the legalization makes heavy use of
EXTRACT_SUBVECTOR.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D97194