[all-commits] [llvm/llvm-project] 87dbcd: [CodeGen] Canonicalise adds/subs of i1 vectors usi...

[david-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 87dbcd88651a4e72fc8f5e1594f9b02232277301
      https://github.com/llvm/llvm-project/commit/87dbcd88651a4e72fc8f5e1594f9b02232277301
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2021-02-25 (Thu, 25 Feb 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    A llvm/test/CodeGen/AArch64/sve-pred-arith.ll
    M llvm/test/CodeGen/X86/avx512-mask-op.ll
    M llvm/test/CodeGen/X86/avx512bw-mask-op.ll

  Log Message:
  -----------
  [CodeGen] Canonicalise adds/subs of i1 vectors using XOR

When calling SelectionDAG::getNode() to create an ADD or SUB
of two vectors with i1 element types we can canonicalise this
to use XOR instead, where 1+1 is treated as wrapping around
to 0 and 0-1 wraps to 1.

I've added the following tests for SVE targets:

  CodeGen/AArch64/sve-pred-arith.ll

and modified some X86 tests to reflect the much simpler codegen
required.

Differential Revision: https://reviews.llvm.org/D97276