[all-commits] [llvm/llvm-project] 78b6d7: AMDGPU: Add even aligned VGPR/AGPR register classes

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 78b6d73a93fc6085d2a2fc84bdce1bbde740cf16
      https://github.com/llvm/llvm-project/commit/78b6d73a93fc6085d2a2fc84bdce1bbde740cf16
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-02-24 (Wed, 24 Feb 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/GCNSubtarget.h
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
    A llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir
    A llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/dpp64_combine.mir
    M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
    M llvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir
    M llvm/test/CodeGen/AMDGPU/reserved-reg-in-clause.mir
    R llvm/test/CodeGen/AMDGPU/reserved-vgpr-tuples.mir
    M llvm/test/CodeGen/AMDGPU/twoaddr-fma-f64.mir
    A llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir

  Log Message:
  -----------
  AMDGPU: Add even aligned VGPR/AGPR register classes

gfx90a operations require even aligned registers, but this was
previously achieved by reserving registers inside the full class.

Ideally this would be captured in the static instruction definitions
for the operands, and we would have different instructions per
subtarget. The hackiest part of this is we need to manually reassign
AGPR register classes after instruction selection (we get away without
this for VGPRs since those types are actually registered for legal
types).


  Commit: 589223e044dbea0554d2e8b54bf49e9cc278b643
      https://github.com/llvm/llvm-project/commit/589223e044dbea0554d2e8b54bf49e9cc278b643
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-02-24 (Wed, 24 Feb 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll
    M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/global-atomics-fp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll

  Log Message:
  -----------
  AMDGPU: Remove special case in shouldCoalesce

Unaligned registers are now constrained with classes, rather than
specially reserving a subset of the whole class.


Compare: https://github.com/llvm/llvm-project/compare/e79cd47e1620...589223e044db